Search - stopwatch vhdl

[VHDL-FPGA-Verilog] time

Description: 电子钟实现包含数字跑表万年历设置三个闹钟时间，日期调整-Clock to achieve with digital stopwatch calendar set three alarm time, date, adjust
Platform: | Size: 2048 | Author: 楚辰 | Hits:

Description: 数字钟：显示，设置时间，设置闹铃（报时），秒表。平台：quartusII 5.1。说明：此版本中已将系统时钟调快，自己稍微改动一下即可，小小的考验，做出来会更有成就感！-digital clock：display time, set time, set alarm(use speaker to alarm), stopwatch. platform: quartusII 5.1 comment: there s a place to change if you want the clock to tick at an actual speed. Find it ,change it and have fun with it!
Platform: | Size: 2020352 | Author: kn | Hits:

[VHDL-FPGA-Verilog] vhd_design

Description: 我学习VHDL的课程设计，是多功能数字钟，有闹钟，秒表等功能，多指教-I learned VHDL course design is multi-functional digital clock, there is an alarm clock, stopwatch functions, multi-Zhi Jiao
Platform: | Size: 349184 | Author: GUO-xc | Hits:

[VHDL-FPGA-Verilog] clock

Description: 采用Verilog HDL语言编写的多功能数字钟，包括四个功能：时间显示与设置、秒表、闹钟、日期显示与设置.-Using Verilog HDL language multi-functional digital clock, including the four functions: time display and settings, stopwatch, alarm clock, date display and settings.
Platform: | Size: 3100672 | Author: 陈涵 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 秒表的verilog语言实现，个人课程设计代码，已验证！实现显示秒，分，时暂停，修正等功能。-Stopwatch' s verilog language implementation, personal curriculum design, code, and has been verified! Implementation show seconds, minutes, suspended, amendment and other functions.
Platform: | Size: 2048 | Author: 张文宝 | Hits:

[VHDL-FPGA-Verilog] Widget_Watch_VHDL

Description: 功能：（1）数字钟（2）数字跑表（3）调整时间 (4)闹钟设置（5）日期设置。设计总体构思：将日期、时钟、秒表及闹钟功能分开实现。选择日期模式，则只显示年、月、日。选择时钟模式，则只显示时、分、秒。选择秒表模式，则只显示秒、毫秒。选择闹钟模式，显示为时、分、秒，另外加一个闹铃。 -Features:(1) digital clock (2) digital stopwatch (3) adjust the time (4) alarm settings (5) date set. The overall design concept: the date,clock, stopwatch and alarm functions to achieve separation.Select a date mode,only displays year,month,day. Select the clock mode, only display hours,minutes,seconds. Select stopwatch mode,only show seconds,milliseconds. Select alarm mode,display too,minutes,seconds,plus an additional alarm.
Platform: | Size: 921600 | Author: | Hits:

[Other] shuzimiaobiaoVHDL

Description: 数字秒表的VHDL语言实现，由于系统定时器8253每秒中断18.2次,利用INT 1AH/00H取得中断次数(DX),得到54.945ms的定时单位。 -Digital stopwatch the VHDL language, because the system timer interrupt 18.2 times per second, 8253, made use of INT 1AH/00H interrupt number (DX), by 54.945ms timing unit.
Platform: | Size: 4096 | Author: 田有林 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 基于fpga的vhdl语言，芯片是ep2c8系列，此代码实现的是秒表显示，毫秒到分的数码管显示，数码管是共阳的，分模块设计的，-The vhdl fpga-based language, the chip is ep2c8 series, this code is implemented stopwatch showed milliseconds to-point digital control, digital control is a total of Yang, the sub-module design,
Platform: | Size: 2525184 | Author: liyu | Hits:

[VHDL-FPGA-Verilog] vhdlcoder

Description: 本文件夹包含了16个VHDL 编程实例，仅供读者编程时学习参考。一、四位可预置75MHz -BCD码（加/减）计数显示器（ADD-SUB）。二、指示灯循环显示器（LED-CIRCLE) 三、七人表决器vote7 四、格雷码变换器graytobin 五、1位BCD码加法器bcdadder 六、四位全加器adder4 七、英语字母显示电路 alpher 八、74LS160计数器74ls160 九、可变步长加减计数器 multicount 十、可控脉冲发生器pluse 十一、正负脉宽数控调制信号发生器pluse width 十二、序列检测器string 十三、出租车计费器spend 十四、数字秒表selclk 十五、抢答器 first -This folder contains 16 examples of VHDL programming, only for readers to learn programming reference. 1, 4 Preset 75MHz-BCD code (plus/minus) count display (ADD-SUB). Second, light cycle display (LED-CIRCLE) 3, seven voting machines vote7 4, Gray code converter graytobin 5, a BCD code adder bcdadder six, four full adder adder4 seven or eight English letter display circuit alpher , 74LS160 counter 74ls160 9, variable-step addition and subtraction counters multicount 10, controllable pulse generator pluse 11, positive and negative pulse width modulation signal generator pluse width of NC 12, sequence detector string 13, a taxi billing spend 14 devices, digital stopwatch selclk 15, Responder first
Platform: | Size: 59392 | Author: 李磊 | Hits:

[VHDL-FPGA-Verilog] 6.1

Description: FPGA实现多功能闹钟，有电子钟、秒表、定时器、电子琴功能-FPGA realization of multi-function alarm clock, which can function as a clock, a stopwatch, a timer,and a piano.
Platform: | Size: 1671168 | Author: f | Hits:

[VHDL-FPGA-Verilog] Stopwatch

Description: Stop-watch for FPGA on 7 segment display
Platform: | Size: 6144 | Author: Aida | Hits:

[VHDL-FPGA-Verilog] vhdl-dianziwannianli

Description: 基于FPGA的电子万年历，此电子万年历系统主要有8个模块分别设计1. 主控制模块 maincontrol 2. 时间及其设置模块 timepiece_main 3. 时间显示动态位选模块 time_disp_select 4. 显示模块 disp_data_mux 5. 秒表模块 stopwatch 6. 日期显示与设置模块 date_main 7. 闹钟模块 alarmclock 8. 分频模块 fdiv -FPGA-based electronic calendar, the electronic calendar system, there are 8 modules are designed for 1. The main control module maincontrol 2. Time and the setup module timepiece_main 3. Time Choice module displays dynamic time_disp_select 4. Display Module disp_data_mux 5. Stopwatch module stopwatch 6. Date display and set the module date_main 7. alarm module alarmclock 8. fdiv frequency module
Platform: | Size: 1024 | Author: 黄枫 | Hits:

[VHDL-FPGA-Verilog] stopwatch

Description: 59.59七段数码管VHDL语言编写秒表-failed to translate
Platform: | Size: 1024 | Author: 王红阳 | Hits:

[Software Engineering] VHDL-maobiao

Description: VHDL秒表，运行过，可以用，供初学者学习-VHDL stopwatch running, you can use for beginners to learn
Platform: | Size: 1969152 | Author: xiaxia | Hits:

[VHDL-FPGA-Verilog] timer

Description: 自己做的计时秒表VHDL语言程序，运行良好，一切俱全。-Own stopwatch VHDL language program, run good, all taste.
Platform: | Size: 2724864 | Author: danie | Hits:

[Software Engineering] CPLD_CODE

Description: 秒表的VHDl软件实现；可调整时间；整点报时；-Stopwatch VHDl software adjustable time whole point of time
Platform: | Size: 670720 | Author: 房贷 | Hits:

[VHDL-FPGA-Verilog] VHDL-stopwatch-reports-and-code

Description: 用VHDL实现数字秒表的设计实践，并用FPGA下载进行功能验证！-Using VHDL the digital stopwatch design practice, and functional verification of FPGA download!
Platform: | Size: 1895424 | Author: 一个好人 | Hits:

[VHDL-FPGA-Verilog] miaobiao

Description: 秒表的VHDL语言程序，是实验课上一个课程设计，非常正确，非常好用。-Stopwatch VHDL language program is the experimental class curriculum design, very correct, very easy to use.
Platform: | Size: 7168 | Author: 塚客 | Hits:

[VHDL-FPGA-Verilog] Digital-stopwatch

Description: 数字秒表，用VHDL语言描述，用层次设计概念，将设计任务分成七个子模块，规定每一模块的功能和各模块之间的接口，然后再将各模块合起来形成顶层文件联试。-Digital stopwatch, using VHDL description, level design concept, the design task is divided into seven sub-module to provide the interface between each module functions and modules, then the modules together to form a top-level file joint trial.
Platform: | Size: 200704 | Author: 黄玲 | Hits:

[Other] A-stopwatch-based-on-FPGA

Description: 基于FPGA的VHDL语言编写的秒表的源程序，需要在FPGA的平台下进行仿真。-A stopwatch written in VHDL language based on FPGA
Platform: | Size: 7168 | Author: 黄伟伟 | Hits:

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[VHDL-FPGA-Verilog] time

[VHDL-FPGA-Verilog] e7v4

[VHDL-FPGA-Verilog] vhd_design

[VHDL-FPGA-Verilog] clock

[VHDL-FPGA-Verilog] clock

[VHDL-FPGA-Verilog] Widget_Watch_VHDL

[Other] shuzimiaobiaoVHDL

[VHDL-FPGA-Verilog] vhdl

[VHDL-FPGA-Verilog] vhdlcoder

[VHDL-FPGA-Verilog] 6.1

[VHDL-FPGA-Verilog] Stopwatch

[VHDL-FPGA-Verilog] vhdl-dianziwannianli

[VHDL-FPGA-Verilog] stopwatch

[Software Engineering] VHDL-maobiao

[VHDL-FPGA-Verilog] timer

[Software Engineering] CPLD_CODE

[VHDL-FPGA-Verilog] VHDL-stopwatch-reports-and-code

[VHDL-FPGA-Verilog] miaobiao

[VHDL-FPGA-Verilog] Digital-stopwatch

[Other] A-stopwatch-based-on-FPGA

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